Ferroelectric capacitors are used in integrated circuit memory devices has become more frequent due to their operation speed, low-power and low-voltage operation, good tolerance and the like. Ferroelectric memory devices can store data when power to the integrated circuit memory device is cut off, i.e. ferroelectric memory devices can be used as non-volatile memory devices. A ferroelectric material provided between electrodes of the ferroelectric memory device may provide the non-volatile properties. The ferroelectric material typically has two polarization states. The polarization state of the ferroelectric material may be changed by applying an electric field and may be retained after the electrical field is no longer applied, i.e. the ferroelectric memory device may store data when the power to the device is cut off.
Similar to the structure of conventional dynamic random access memories (DRAMs) capacitor, ferroelectric capacitors typically include a ferroelectric material between two electrodes. DRAM capacitors store data using a dielectric layer between two electrodes. In contrast, ferroelectric capacitors utilize the polarization property of a ferroelectric material between the two electrodes to store data. Thus, ferroelectric capacitors may be formed using methods of fabrication different from the methods of fabrication used for DRAMs because the ferroelectric capacitor utilizes a new material, i.e., the ferroelectric material, not used in the fabrication process of DRAMs. For example, if polysilicon is used as a material for one of the electrodes of the ferroelectric capacitor, the ferroelectric material may react with the polysilicon. Accordingly, a noble material such as platinum and/or a conductive material such as ruthenium dioxide may be used for the electrodes of ferroelectric capacitors so that a reaction may not occur.
Furthermore, after forming the ferroelectric material, the ferroelectric material may be treated using a thermal process having a high temperature in an oxygen ambient to provide a ferroelectric crystalline structure, i.e., a perovskite structure. During the thermal process, a thin insulation layer, for example, silicon dioxide, may be formed at an interface between a polysilicon contact plug and a lower electrode, which may cause the contact resistance to be degraded. Thus, an oxidation barrier conductive layer may be formed between the contact plug and the lower electrode in conventional devices to reduce the degradation of the contact resistance.
Referring now to FIGS. 1A and 1B, cross-sections of conventional ferroelectric capacitors will be discussed. As illustrated in FIG. 1A, an insulation layer 10 is formed on an integrated circuit substrate (not shown). A polysilicon contact plug 12 is provided in the insulation layer 10 so as to electrically connect an active region of the integrated circuit substrate (not shown) to an oxidation barrier conductive layer 14. The oxidation barrier conductive layer 14 is provided on the insulation layer 10 and the contact plug 12. A lower electrode layer 16 is provided on the oxidation barrier conductive layer 14. A ferroelectric layer 18 is provided on the lower electrode and an upper electrode layer 20 is provided on the ferroelectric layer 18.
Referring now to FIG. 1B, the oxidation barrier conductive layer 14, the lower electrode layer 16, the ferroelectric layer 18 and the upper electrode layer 20 are etched to form a capacitor 22. As illustrated in FIG. 1B, the ferroelectric capacitor 22 may have an inclined sidewall profile, which may be caused by electrode layers that are not typically easily etched and/or thick material layers. Accordingly, the ferroelectric capacitor 22 may be unintentionally electrically connected to an adjacent ferroelectric capacitor. This potential problem may be addressed by increasing a distance between adjacent cells, however, this may reduce the number of cells that may be integrated on a single chip. Furthermore, inclined sidewalls of the ferroelectric layer 18 may decrease an area directly contacting the upper electrode, thereby reducing the contact resistance of the device.
Furthermore, to decrease the likelihood of having inclined sidewalls as illustrated in FIG. 1B, the thicknesses of the oxidation barrier conductive layer 14, the lower electrode layer 16, the ferroelectric layer 18 and/or the upper electrode layer 20 may be decreased. However, decreasing the thickness of the oxidation barrier conductive layer 14 may cause a surface of the contact plug 12 to be unintentionally oxidized, thus, possibly increasing the contact resistance of the device. Furthermore, decreasing the thickness of the lower electrode layer 16 may make it difficult to provide a ferroelectric material having an acceptable crystalline property because the crystalline property of the ferroelectric material may depend on the lower electrode layer 16. In addition, when the oxidation barrier conductive layer 14, the lower electrode layer 16, the ferroelectric layer 18 and the upper electrode layer 20 are etched to form the capacitor 22, the ferroelectric layer 18 may be over etched by the etchant such that the properties of the ferroelectric material may be degraded. Furthermore, after the ferroelectric layer 18 is etched, the ferroelectric layer 18 may be exposed to an etching ambient, for example, a plasma gas, which may also damage the ferroelectric material. It will be understood that the damage caused during the etch may occur even if the layers 20, 18, 16, 14 are etched in separate steps. Accordingly, improved ferroelectric capacitors and methods of fabricating ferroelectric capacitors may be desired.